High speed serial bus interfaces, such as universal serial bus (USB) interfaces, have become increasingly important as data hungry peripheral devices have proliferated. The serializer-deserializer (SerDes) at the heart of a serial bus interface transfers data between a serial data channel and a parallel data bus, such as the internal system bus serving a CPU motherboard. For a typical serial port connected to a computer, the SerDes (serializer direction) takes data from the computer's parallel system bus and puts the data onto the serial communication channel (i.e., serializes the data). Similarly, for input data, the SerDes (deserializer direction) takes the data off the serial channel and puts the data onto the computer's parallel system bus (i.e., deserializes the data). Computer engineers are continually striving to increase SerDes data transfer rates, improve reliability, and decrease costs.
A high speed SerDes interface implements a clock and data recovery (CDR) phase locking stage to synchronize the interface to the serial data rate. During the CDR phase locking stage, the SerDes data sampling controller detects and locks onto the source data rate and phase timing, which is typically set by the clock rate of the host computer that created the data stream. Once phase locking stage has been achieved, high speed data transfer (deserialization) proceeds during the data transfer stage. The time period during which the error free data bits can be reliably detected (referred to as the serial eye) shrinks as the data transfer rate approaches the physical limits of the underlying data channel. It therefore becomes increasingly difficult, in general, to lock onto the serial data stream as the data transfer rates increase.
During the data transfer stage, adaptive decision feedback equalization (DFE) facilitates data bit detection by compensating for inter-symbol interference (ISI) incurred in the serial data channel. [Transition and data sampling time skew is mostly used to compensate for data eye distortion after DFE adaptation]. SerDes phase locking problems can be exacerbated by the DFE adaptation functionality, which tends to skew (phase shift) the timing of the transition sampling phase away from the time-based center of the unit interval in order to achieve the best vertical eye opening at the data sampling point. At high data transfer rates, the data eye can become substantially shifted as a result of DFE induced phase sample skew moving the transition sample phase toward the periphery of the serial data eye. In this situation, DFE adaption can significantly degrade the ability of the CDR to achieve a low error rate in the recovered serial data stream.
There is, therefore, a continuing need for improved techniques for SerDes phase locking and, more particularly, a need to mitigate the adverse effects that DFE adaption can have on CDR phase locking in SerDes interfaces.